LAYERS 7 - Challenges In 3D IC and Heterogeneous Integration

Thin film technology solutions for Front End Integration

Chip makers face more and more challenges for enabling 3D IC and/or heterogeneous integration into all type of different module packages with increased packing performance and functional density. Not only must they manage thermal wafer budget, but also the wafer shape as flatness becomes a more and more important prerequisite. Evatec’s BU Semiconductor Senior Project Leader, Riccardo Morciano and Dr. Reinhard Benz, Head of Strategic Sales & Marketing illustrate just one example of the production solutions helping lead the way in advanced CMOS fabs.

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